The Unibone emulates a PDP 11/20 CPU. This is the very first PDP-11 CPU, the KA11, and it lacks a lot of instructions that were present on later machines. This is a pity, because it limits what the Unibone can run: code that uses the later instructions will fail. This is particularly sad for a great use case for this wonderful thing which is to test hardware: some XXDP tests fail because they use these instructions. I had this happening while I wanted to test the DELUA adapter, and I decided to try to add the missing instructions to the Unibone.
Work in progress, incomplete
Implementing the first set: the EIS instructions
The Extended Instruction set, implemented in part for the 11/20 by the KE11-A extension, added the following instructions in the 007x000 range: ASH, ASHC, MUL, DIV. Later CPUs added XOR to this list.
I implemented these by adding a parameter “extended_inst” to the cpu20 device. When set the code now emulates these instructions.
Testing the EIS instructions
The 11/34 (KD11-B) implements these instructions, and there is a specific test for them, details here. The FKAC test tests these EIS instructions, so, let’s run it. Sadly enough it halts “CPU Halt by instruction” at 000014. I enabled Trace level on the Unibone, and the log (dbg s) shows:
[22:02:01.655324 Dbg cpu 02267@ka11.c:0412] EXEC [000620] MOV [22:02:01.655328 Dbg cpu 02267@ka11.c:0161] DATI [000622] => 000004 [22:02:01.655331 Dbg cpu 02267@ka11.c:0161] DATI [000004] => 000006 [22:02:01.655335 Dbg cpu 02267@ka11.c:0161] DATI [000576] => 000000 [22:02:01.655338 Dbg cpu 02267@ka11.c:0174] DATO [000576] <= 000006 [22:02:01.655346 Dbg cpu 02267@ka11.c:0161] DATI [000624] => 013746 [22:02:01.655350 Dbg cpu 02267@ka11.c:0412] EXEC [000624] MOV [22:02:01.655353 Dbg cpu 02267@ka11.c:0161] DATI [000626] => 000006 [22:02:01.655357 Dbg cpu 02267@ka11.c:0161] DATI [000006] => 000000 [22:02:01.655360 Dbg cpu 02267@ka11.c:0161] DATI [000574] => 000576 [22:02:01.655363 Dbg cpu 02267@ka11.c:0174] DATO [000574] <= 000000 [22:02:01.655370 Dbg cpu 02267@ka11.c:0161] DATI [000630] => 012767 [22:02:01.655374 Dbg cpu 02267@ka11.c:0412] EXEC [000630] MOV [22:02:01.655377 Dbg cpu 02267@ka11.c:0161] DATI [000632] => 000644 [22:02:01.655381 Dbg cpu 02267@ka11.c:0161] DATI [000634] => 177146 [22:02:01.655385 Dbg cpu 02267@ka11.c:0161] DATI [000004] => 000006 [22:02:01.655388 Dbg cpu 02267@ka11.c:0174] DATO [000004] <= 000644 [22:02:01.655395 Dbg cpu 02267@ka11.c:0161] DATI [000636] => 005777 [22:02:01.655399 Dbg cpu 02267@ka11.c:0671] EXEC [000636] TST [22:02:01.655402 Dbg cpu 02267@ka11.c:0161] DATI [000640] => 177640 [22:02:01.655406 Dbg cpu 02267@ka11.c:0161] DATI [000502] => 177570 [22:02:01.655409 Dbg cpu 02267@ka11.c:0161] DATI [177570] => 000000 [22:02:01.655415 Dbg cpu 02267@ka11.c:0161] DATI [000642] => 000407 [22:02:01.655419 Dbg cpu 02267@ka11.c:0722] EXEC [000642] BR [22:02:01.655425 Dbg cpu 02267@ka11.c:0161] DATI [000662] => 012637 [22:02:01.655428 Dbg cpu 02267@ka11.c:0412] EXEC [000662] MOV [22:02:01.655432 Dbg cpu 02267@ka11.c:0161] DATI [000574] => 000000 [22:02:01.655435 Dbg cpu 02267@ka11.c:0161] DATI [000664] => 000006 [22:02:01.655439 Dbg cpu 02267@ka11.c:0161] DATI [000006] => 000000 [22:02:01.655442 Dbg cpu 02267@ka11.c:0174] DATO [000006] <= 000000 [22:02:01.655450 Dbg cpu 02267@ka11.c:0161] DATI [000666] => 012637 [22:02:01.655453 Dbg cpu 02267@ka11.c:0412] EXEC [000666] MOV [22:02:01.655457 Dbg cpu 02267@ka11.c:0161] DATI [000576] => 000006 [22:02:01.655460 Dbg cpu 02267@ka11.c:0161] DATI [000670] => 000004 [22:02:01.655464 Dbg cpu 02267@ka11.c:0161] DATI [000004] => 000644 [22:02:01.655467 Dbg cpu 02267@ka11.c:0174] DATO [000004] <= 000006 [22:02:01.655474 Dbg cpu 02267@ka11.c:0161] DATI [000672] => 106427 [22:02:01.655478 Dbg cpu 02267@ka11.c:0800] TRAP 10
So, an illegal instruction.
Looking at the EXEC parts we can see the instructions being executed and their address. The last one that worked was a MOV at 000666, the DATI before the trap shows a read of 000672 with opcode 106427.
The fiche database only contains a fiche for “DFKACA”, and I cannot match the above execution with its content:
But there is an instruction there with the same opcode, at 000620: MTPS. Which is according to the docs a LSI11 only instruction which moves a word to the PSW. It has an accompanying read called MFPS. This is odd because the 11/34 is not a LSI11 CPU, but the test’s documentation says:
So, apparently the 11/34 implemented that MTPS instruction. Sigh.
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